Complementary metal-oxide-semiconductor (CMOS) technology refers to both integrated circuits and the processes used to make integrated circuits. CMOS processes are generally carried out at CMOS foundries to make integrated circuits in silicon wafers or substrates. During a typical CMOS process, thousands to billions of field-effect transistors and other electronic devices can be formed in a single substrate by selectively etching, doping, and depositing different layers of metal, semiconductor, and dielectric materials on the substrate as well as etching and doping the substrate itself. Once the processing is complete, the substrate is then diced into individual chips, which can be packaged for use in electronic components.
In some cases, the integrated circuits include photonic components in addition to or instead of electronic components. Unfortunately, however, integrating optical waveguides into silicon substrates using standard CMOS processes has proven difficult for a number of reasons. For instance, although silicon transmits near-infrared light, it must be surrounded with a low-index material, such as silica (silicon dioxide) or another dielectric, to act as a waveguide. And silicon absorbs visible light, making it unsuitable for guiding visible light.
Unfortunately, conventional bulk CMOS manufacturing processes do not involve forming a single-crystalline silicon layer clad in a dielectric with a lower refractive index. To compensate for this lack, others have suggested depositing and patterning waveguides on top of the existing CMOS process layers instead of making changes to the conventional bulk CMOS manufacturing processes. But depositing and patterning waveguides on top of the existing CMOS process layers involves complicated processing and high resolution lithography on top of the complicated, non-planar film stack of the full electronic manufacturing process. Unfortunately, typical lithography steps in this part of the CMOS process are performed via I-line steppers to increase the depth of field, which may significantly reduce the available pattern resolution for the waveguide layer. Further, the additional steps required to deposit and pattern the waveguides may be expensive to develop and perform.
Besides the aforementioned fabrication complexity, depositing and patterning waveguides on top of the existing CMOS process layers also yields thick dielectric layers on top of the entire electronic chip. These thick dielectric layers degrade the chip's effective thermal conductance, decreasing its total allowable power dissipation and, as a result, limiting its maximum operation temperature. Additionally, the chip's power and communications typically pass through these thick dielectric layers, resulting in an undesired increase in the total inductance of the chip's power network and in the capacitance of the chip's signaling paths.
The dielectric layer can also be deposited underneath a silicon waveguide layer, e.g., as in silicon-on-insulator (SOI) waveguides. In a typical SOI waveguide, a layer of silicon is formed into a rib on top of a buried oxide layer (typically silicon dioxide) which in turn is on a silicon substrate. Although SOI rib waveguides are well known, they tend to be relatively expensive compared to conventional bulk CMOS devices; in some cases, an unprocessed SOI wafer can cost as much as a fully processed CMOS wafer. SOI CMOS processing is also available in only about 5% of CMOS foundries. And because silicon absorbs light at wavelengths below about 1100 nm, even SOI rib waveguides are unsuitable for guiding visible light.